Capgemini
Roles & Responsibilities Define system and SoC architecture. Translate product requirements into clear technical specifications. Drive full-chip and subsystem microarchitecture including compute, memory, NoC, high-speed interfaces, interconnect, security, and power subsystems. Develop architecture trade-off studies covering PPA, cost, scalability, and roadmap fit. Guide RTL, design verification, DFT, physical design, firmware, and system teams through architecture alignment and execution. Own architecture reviews and lead customer technical discussions. Create architecture documentation and Golden RTL acceptance criteria. Support roadmap planning, platform reuse, and derivative strategies. Our Ideal Candidate
15+ years of experience in ASIC/SoC development. Proven experience delivering multiple SoCs from specification to silicon. Strong architecture and microarchitecture expertise for full chip and subsystem domains. Hands-on experience with ARM and/or RISC-V based systems. Deep knowledge of interconnect protocols and fabrics such as AXI, AHB, CHI, and NoC. Experience with HBM/HMC memory systems. Strong understanding of clock architecture, power architecture, and performance optimization. Hands-on capability in Verilog/SystemVerilog. Strong customer-facing communication, architecture review, and technical decision-making skills. Ability to support and deliver multiple projects simultaneously. Good to Have Chiplet/UCIe architecture exposure. Experience with Arteris and ARM NoC solutions. Exposure to AI/ML accelerators and HPC architecture. Security architecture knowledge. Functional Safety exposure, including ISO 26262. Performance simulation/modeling using SystemC and/or Python. Knowledge of advanced technology nodes, including 5nm and below.