ASIC Engineer | RTL Design, Verilog, System Verilog | CDC, Lint | Exp - 4 to 7 years | Bangalore

Exciting opportunity for an ASIC Engineer to lead RTL design and system verification within Cisco's Enterprise and Service Provider solutions. Drive high-performance ASIC development, architect solutions, and optimise logic for low power and area. Ideal for candidates with significant ASIC engineering experience and expertise in RTL design.